Computer architectures frequently use specific protocols in performing and managing various processor and system level tasks. The protocols may require that an architecturally elder condition or set of conditions be met before an architecturally younger processing step may proceed. In one example, to ensure proper alignment in time between the elder condition and younger step, a DRAIN instruction is placed in the beginning of an instruction stream, i.e., before any instruction potentially required to adhere to such protocols. This ensures architecturally correct operation.
The architectural tasks requiring such protocols depend on the architectural level. There are general architectures available to programmers that describe tasks, such as instruction level exception reporting or system wide alterations, among many others that are to adhere to such protocols. There are also machine dependent internal microarchitectures restricted to proprietary internal code describing conditions required to implement complex higher level architectural tasks. The DRAIN instruction can be made available to either level architecture, as a particular processor development team deems necessary.
To maximize performance, pipelined processors are employed that do not wait to establish an architectural state associated with completely processing one instruction before processing is begun on a subsequent instruction. Processing of several instructions overlap in time. The work required to process an instruction in its entirety is divided into several common and basic steps. Each step corresponds to a pipeline stage. As an instruction proceeds through the processor, it advances to the next pipeline stage. Each stage may contain one or more instructions. Each pipeline stage overlaps with other pipeline stages. As a result, there can be many instructions at any particular point in time at various stages of execution. The pipelining of instructions has eliminated the point in time defined as an architectural state between instructions. Thus, the DRAIN instruction is used to reestablish architectural separation in time, if necessary, between an elder condition or an event of interest and a subsequent processing step.
As processor frequency has increased, the number of pipeline stages has increased. The pipeline stage a particular DRAIN instruction is to protect depends on the chosen condition(s) to monitor. The further the required stage to protect is from the stalled stage (at the beginning of the instruction stream) the more performance is degraded. With more pipeline stages, there are more stages to consider protecting and they are farther apart, in number of processor cycles, than previously. Another effect of increased processor frequency is an increase in the number of cycles required to communicate status between some, but not all, functional entities. Furthermore, the exact definition of status transmission delay may not be known early in the hardware design phase.